![]() “It will go much further than that in the near future.” Using the technology only for power delivery “is just the first step for us,” says Knowles. GraphcoreĪlthough the new product has no transistors on the power-delivery chip, those might be coming. Signals and power pass through the top chip from solder bumps. TSMC’s wafer-on-wafer stacking results in a processor chip connected to a power-delivery chip by copper pads. Any duds can be cut off from the rest of the IPU by means of built-in fuses, says Nigel Toon, Graphcore cofounder and CEO. Like some other new AI processors, the IPU is made up of many repeated, and therefore redundant, processor cores and other parts. Graphcore’s way around this is to let it happen, to a degree. Bonding two wafers would then as much as double the resulting number of flawed chips. That is, there are always a few chips in a batch of wafers that are flawed. However, one long-standing concern with this technique was the “known good die” problem. Graphcore executives say wafer-on-wafer technology results in a higher density of connections between the chips than attaching individual chips to a wafer. With the power chip, it can reach that clock-rate and consume less power, too. Without the power-delivery chip, the IPU would have to increase its operating voltage above its nominal level to work at 1.85 GHz, consuming a lot more power. By placing these reservoirs of charge so close to the transistors, power delivery is smoothed out, allowing the IPU cores to run faster at lower voltage. These components are formed in deep, narrow trenches in the silicon, exactly like the bit-storing capacitors in DRAM. It’s the capacitors that really make the difference. The latter make power and data connections that pass through the power chip to the processor die. ![]() Instead, they are packed with capacitors and vertical connections called through-silicon vias. These chips carry no transistors or other active components. The other wafer had a corresponding set of power-delivery chips. These processors were already in use in commercial systems and made a good showing in the last round of MLPerf benchmark tests. In Graphcore’s case, one wafer is full of the company’s second generation AI processor (the company calls them IPUs, for intelligence processing units) with 1,472 IPU cores and 900 megabytes of on-chip memory. The top wafer is then thinned down to just a few micrometers and the bonded wafer is diced up into chips. “You can think of this as a kind of cold weld between the pads,” says Knowles. When the two wafers are pressed together, the pads fuse. The chips on each have copper pads that match up when the wafers are aligned. ![]() In TSMC’s SoIC WoW technology, two entire wafers of chips are bonded. In other 3D-chip-stacking technology, such as Intel’s Foveros, already excised chips are attached to other chips or to wafers. The new systems are up to 16 percent more efficient at training key neural networks. Both Bow and its predecessor the Colossus MK2 were made using the same manufacturing technology, TSMC’s N7.Ĭompared with Graphcore’s previous generation, the new computers can train key neural networks about 40 percent faster. “We are entering an era of advanced packaging in which multiple silicon die are going to be assembled together to supplement the performance advantages we can get from increasing progress along an ever-slowing Moore’s Law path,” says Simon Knowles, Graphcore chief technical officer and cofounder. Importantly, users get this improvement with no change to their software at all. That translates to computers that train neural nets up to 40 percent faster with as much as 16 percent less energy compared to its previous generation. The addition of the power-delivery silicon means Bow can run faster-1.85 gigahertz versus 1.35 GHz-and at lower voltage than its predecessor. The new combined chip, called Bow, for a district in London, is the first on the market to use wafer-on-wafer bonding, say Graphcore executives. The secret was to use TSMC’s wafer-on-wafer 3D integration technology during manufacture to attach a power-delivery chip to Graphcore’s AI processor. U.K.-based AI computer company Graphcore made a significant boost to its computers’ performance without changing much of anything about its specialized AI processor cores.
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